1. Field of the Invention
The present invention relates to semiconductor devices and particularly to semiconductor devices including memory cells to and from which data is written and read, respectively, in accordance with voltage supplied.
2. Description of the Background Art
There has been developed a nonvolatile semiconductor memory device including a floating gate (FG) that can receive electrons or have electrons removed therefrom to store information, such as a semiconductor device having flash memory incorporated therein. Flash memory includes memory cells having a floating gate, a control gate (CG), a source, a drain, and a well or substrate. The memory cell has a threshold voltage, which increases when the floating gate receives electrons, and decreases when the floating gate has electrons removed therefrom (see Japanese Patent Laying-open No. 2004-164811 for example.)
Generally, when a memory cell has a threshold voltage falling within the lowest voltage distribution, the memory cell is in an erased state. Furthermore, when the memory cell has a threshold voltage falling within a distribution higher than the erased state, the memory cell is in a written state. For example, if the memory cell stores two bits of data, the threshold voltage distribution lowest in voltage corresponds to a logic level “11” and this state is referred to as an erased state. The memory cell is subjected to a write operation and has a threshold voltage rendered higher than the erased state to obtain threshold voltages corresponding to logic levels “10”, “01” and “00”. This state is referred to as a written state.
Although it does not have flash memory incorporated therein, Japanese Patent Laying-open No. 2002-350500, for example, discloses such a semiconductor device as follows: More specifically, a charge pump circuit in operation supplies an internal voltage line with negative electrical charge to decrease negative internal voltage. A voltage division circuit generates a control voltage in accordance with a difference in voltage between a first positive voltage received in a test mode externally at an input terminal and internal voltage. A comparison circuit causes the charge pump circuit to operate in accordance with a result of comparing a second positive voltage received in the test mode externally at an input terminal with the control voltage. The second positive voltage is set in accordance with a target negative internal voltage. By such configuration, externally input negative voltage can be prevented by a protection diode from being applied to an internal circuit, and negative voltage can be generated in the internal circuit and used in the test mode.
Flash memory incorporated semiconductor devices have their flash memory modules tested by measuring their memory cells' threshold voltage. More specifically in this test a read voltage is supplied from a pad of the semiconductor device to a memory cell of a flash memory module and the read voltage is gradually increased. A read voltage that allows data stored in the memory cell to be read is the memory cell's threshold voltage.
Furthermore, to be more reliable, semiconductor devices have a surge protection circuit connected to a pad thereof. The semiconductor devices are tested for reliability by measuring surge endurance. If the semiconductor device has a flash memory module sharing a pad with a microcomputer or a similar circuit that requires surge protection, the surge protection circuit is also connected to the pad. In that case, when a memory cell's threshold voltage is to be measured, a read voltage will be supplied to the pad to which the surge protection circuit is connected. The surge protection circuit clamps a voltage exceeding a predetermined value, and if the read voltage exceeds the predetermined value, it cannot be supplied to the memory cell, and the memory cell's threshold voltage cannot be measured. Conventional semiconductor devices thus disallow a surge protection circuit to be connected to a pad required to receive high voltage, and are thus difficult to be enhanced in reliability.
Furthermore, the semiconductor device of Japanese Patent Laying-open No. 2002-350500 requires two external input terminals to generate a negative voltage used in the test mode. The semiconductor device is thus difficult to miniaturize.